Chinese Academy of Sciences releases domestic open source RISC-V processor “Xiangshan”: The first version is scheduled to be released in July

IT Home June 23 News The first RISC-V China Summit was held this week at Shanghai University of Science and Technology. At this conference, Bao Yungang, a professor at the University of Chinese Academy of Sciences and a researcher at the Institute of Computing Technology of the Chinese Academy of Sciences, released a domestic open source high-performance RISC-V Processor core-Xiangshan. He said that there is currently no open source mainline like Linux in the CPU field, so the R&D team judges that the industry needs an open source high-performance RISC-V core that can be widely used in the industry and can support the academia to experiment with innovative ideas. The goal is to survive at least 30 years like Linux. With the support of the Institute of Computing Technology of the Chinese Academy of Sciences and Pengcheng Laboratory, Xiangshan has developed an open source high-performance RISC-V processor core through the China Open Instruction Ecology (RISC-V) Alliance and industry companies. The first mass-produced version “Yanqi” “Lake” plans to tape out in July this year, using TSMC’s 28nm process. Bao Yungang said that after more than a year of preparatory work, the project established a team and applied for funding. On June 11, 2020, Xiangshan established a code repository on GitHub. In one year, 25 classmates and teachers participated in the development of Xiangshan, and submitted 3296 codes, with a total of more than 50,000 lines and more than 400 documents. Xiangshan is an open source RISC-V processor core, its architecture code name is named after the lake. The first version of the architecture is codenamed “Yanqi Lake”. The RTL code for this processor was completed in April 2021, and it is scheduled to be taped out in July based on TSMC 28nm process. The current frequency is 1.3GHz. The second edition of the framework is codenamed “Nanhu”, which is a tribute to the 100th anniversary of the founding of the party. “Nanhu” plans to tape out by the end of this year, and will use SMIC’s 14nm process with a target frequency of 2GHz. Specifically, the “Yanqi Lake” architecture is an out-of-order processor core with 11 stages of pipeline, 6 launches, and 4 memory access components. The launch width is already comparable to some ARM high-end processor cores, but it has not been fully optimized, so there is still a big gap in actual performance. Professor Yungang Bao’s team hopes that through continuous iterative optimization (“Nanhu”–> “X Lake”–> “Y Lake”–> …) in the future, the performance will reach the level of ARM A76. In 2020, the team completed a test tape out of an 8-core tagged RISC-V processor based on Chisel, using TSMC’s 28nm process. The R&D staff built a set of process-oriented automatic regression test framework based on GitHub CI. Starting from September 2020, this test chip has successfully started the Linux/Debian system on the FPGA. One of the important decisions for the development of the “Xiangshan” processor core was to choose the agile design language Chisel, because the development efficiency is much higher than that of Verilog, and the same function is realized. The amount of Chisel code is only 1/5 of Verilog. Another important decision in the development process of “Xiangshan” is to attach great importance to building processes and tools that support agile design. This provides a scientific process for chip development and ensures the success rate. In addition, the R&D team has developed more than a dozen unique tools to support this agile design process. IT Home understands that Xiangshan is currently developing the next-generation architecture “South Lake”. The goal is to tape out by the end of this year. Based on SMIC’s 14nm process, the frequency will reach 2GHz, and the SPECCPU score will reach 10 cents/GHz, supporting dual channels DDR memory and more functions such as PCIe, USB, HDMI, etc. According to the official, the research and development of the Xiangshan processor core is supported by Beijing Zhiyuan Artificial Intelligence Research Institute and senior experts from Beijing Microcore. In the second phase, it will also be jointly developed with partners such as ByteDance, ESWIN, and Unisilicon Technology.